The present invention relates to a semiconductor device and a method for fabricating the same, more specifically, a semiconductor device including MIS transistor in which the threshold voltage is controlled by a substrate bias, and a method for fabricating the semiconductor device.
As semiconductor device is more downsized and higher integrated, MIS transistor is required to be more speedy and have lower operation voltages.
For higher speed of a MIS transistor, it is effective to constitute the MIS transistor to have a low threshold voltage and make a drive voltage to be applied to the drain higher. That is, the drive force of the MIS transistor depends on a voltage difference between the drive voltage to be applied to the drain and a threshold voltage thereof, and as the voltage difference is larger, the operation speed can be higher.
On the other hand, when the threshold voltage of the MIS transistor is decreased, the off-current, i.e., the leakage current at the off state is increased. Accordingly, to decrease the leakage current, it is necessary to make the threshold voltage high to some extent.
To satisfy such requirements, which are incompatible with each other, conventionally in semiconductor devices, substrate bias is applied to thereby change the threshold voltage. The substrate bias is a voltage to be applied to a well where the MIS transistor is formed and is a voltage of the polarity opposite to that of a voltage to be applied to the gate electrode. A voltage of the polarity opposite to a voltage to be applied to the gate electrode is applied to the channel region via the well, whereby the inversion voltage of the channel is increased. Accordingly, the substrate bias is controlled, whereby the threshold voltage can be changed.
When the MIS transistor operates, no substrate bias or a substrate bias of low voltage is applied to thereby make the threshold voltage low while driving the MIS transistor at high drive voltage. Thus, the voltage difference between the drive voltage and the threshold voltage can be made large, and the high speed operation can be made possible. When the MIS transistor is not operated, a substrate bias of high voltage is applied to thereby make the threshold voltage high, and the leakage current can be decreased.
The related arts are disclosed in, e.g., Reference 1 (Japanese published unexamined patent application No. Hei 10-074941), Reference 2 (Japanese published unexamined patent application No. Hei 11-354785), and Reference 3 (M. Togo et al., “Power-aware 65 nm Node CMOS Technology Using Variable VDD and Back-bias Control with Reliability Consideration for Back-bias Mode”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 88-89).